This invention relates to the fabrication of single metallization p-channel and n-channel enhancement mode field-effect transistors of the periodic table group III-V material type and to the fabrication of a form of such devices capable of coexistence in a single wafer of semiconductor material.
The invention provides an enhancement mode p-channel field-effect transistor in which a single metallization step realizes the Schottky barrier gate contact and the ohmic junction source/drain contacts--a single metallization arrangement enabled in part by an unusual sequence of masking operations. The invention arises from compromise between several semiconductor device disciplines--including material growth, device metallization, and material deposition. The achieved field-effect transistor is technically and economically viable for use in digital and analog transistor applications including complementary transistor pairs in uses extending into the microwave frequency range.
Several concepts appearing in the present invention also appear in the patent and publication literature as stand-alone concepts, concepts used in a different setting or concepts combined in less than the combination contemplated in the present invention. The present invention is, however, believed to represent a novel and unobvious combination of such concepts to achieve a useful result. The concept of using the same metal in parts of the source, drain and gate structure of a field-effect transistor, for example appears in a certain form in transistors fabricated some years ago when the self aligned gate structure was new in the art. Examples of this same metal usage appear, for example in the two related RCA patents of Napoli et al., U.S. Pat. No. 3,764,865 and U.S. Pat. No. 3,861,024. The same metal concept also appears in the two related Westinghouse patents of Kim, U.S. Pat. No. 3,855,690 and U.S. Pat. No. 3,943,622.
In each of these four patents, however, the disclosed transistor involves use of a common metal to connect to an already formed source/drain ohmic contact and to form the Schottky barrier gate contact. In the silicon material used in the devices of these four patents an ohmic contact is moreover achieved with the mere addition of another layer of material and does not require the alloying, annealing and other complexities used for group III-V semiconductor device ohmic contacts. The present invention is believed distinguished over the disclosure of these older patents by its use of the same metal to actually form the gate contact as to form the source/drain contacts of the transistor. Moreover, in the present invention these source/drain contacts are achieved in a non-alloyed fashion in both the p-channel and n-channel devices of a complementary pair.
The U.S. Pat. No. 4,961,194 of S. Kuroda et al., describes gallium arsenide MESFET and HEMT devices which use the combination of non-alloyed ohmic contacts, same metal electrodes, acetone solvent removal of photoresist coatings, ion implanted device separation areas and selective etching. Although each of these features may be used in the present invention, additional practices not disclosed in the Kuroda et al. patent are also a part of the present invention and provide significant distinction over the Kuroda et al. disclosure. The Kuroda etching aluminum patent, for example, does not disclose the use of a permanent secondary mask and passivation material layer nor the use of a gate aperture recess received in a gate window as is accomplished in applicants' invention. In view of the similar areas of work and in the interest of minimizing the size of the present patent document, the contents of the of S. Kuroda et al. U.S. Pat. No. 4,961,194 patent are hereby incorporated by reference herein.
An article published in the technical literature some years ago is also of interest with respect to the single metal utilization and is additionally of interest with respect to the use of non-alloyed ohmic contacts in a field-effect transistor. This article, "A New Fabrication Technology for AlGaAs/GaAs HEMT LSI's Using InGaAs Non-alloyed Ohmic Contacts", is authored by S. Kuroda et al., apparently the same S. Kuroda et al., as appears in the above identified U.S. Pat. No. 4,961,194 and appears at page 2196 in the Institute of Electrical and Electronic Engineers Transactions on Electron Devices, Volume 36, number 10, October, 1989. This Kuroda article is in fact of an especially enlightening contrast in nature with respect to the present invention since it teaches the use of a complex etching sequence during formation of the transistor elements and the present invention avoids use of this sequence in favor of a more practical and less costly procedure.
In a somewhat related situation the technical article "All-Refractory GaAs FET Using Amorphous TiWSi.sub.x Source/Drain Metalization and Graded In.sub.x Ga.sub.1-x As Layers" authored by N. Papanicolaou which appears at page 7 in the Institute of Electrical and Electronic Engineers Electron Devices Letters, volume 15, number 1, January, 1994 discloses the use of non-alloyed alloyed ohmic contacts in a gallium arsenide field-effect transistor. The Papanicolaou article however, relates to the fabrication of a high temperature field-effect transistor device, a device having refractory metal elements and involving the use of Tungsten metal. The Papanicolaou article also presents an informative discussion of the non-alloyed ohmic contact art.
The inventors of the present invention have also found the textbook "Modern GaAs Processing Methods" authored by Ralph Williams, Artech House, of Boston and London, to be of assistance in explaining and understanding certain aspects attending the present invention including its relationship with the prior art. In the further interest of minimizing the size of the present patent document, the contents of the Ralph Williams, Artech House textbook are therefore hereby incorporated by reference herein.
Although each of these documents from the prior art may relate to an aspect of the present invention it is believed that the invention as described herein represents the first combination of the plurality of concepts and compromises necessary to achieve a successful single metal, non-alloyed contact, selective etching-achieved, and secondary mask-inclusive enhancement mode field-effect transistor.
Non-alloyed ohmic contacts and other features relating to the present invention are additionally disclosed in several technical articles as follows.
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Bozada, "A Combined Electron Beam/Optical Lithography Process Step for the Fabrication of Sub-Half Micron-Gate-Length MMIC Chips", Fourth National Technology Transfer Conference, National Aeronautics and Space Administration, Publication Number 3249, 1993, pp 54-59. PA1 depositing over said semiconductor wafer a secondary mask dielectric material layer; PA1 forming, through a selected region of said secondary mask dielectric material layer, source and drain current conductive paths for said field-effect transistor, said conductive paths comprising doped semiconductor material regions orthogonally traversing a plurality of said semiconductor material layers and terminating in source and drain elements disposed in a channel layer of said semiconductor material layers; Dependent claims: by ion implanting; silicon nitride acting as implant screen to give dopant concentration peak at ohmic layer surface and low contact resistance; p-channel material formed PA1 electrically activating said source and drain conductive paths with a rapid thermal anneal sequence; PA1 forming orthogonally oriented electrical isolation regions surrounding said transistor and intermediate said transistor and any other transistors in said wafer; PA1 removing a gate window portion of said secondary mask dielectric material layer to form a gate window access to an uppermost of said semiconductor material layers, an access bounded in a transistor channel length direction by disposition between said source and drain conductive paths; PA1 defining, within said secondary mask dielectric material layer gate window, a small dimension gate region aperture through said uppermost semiconductor material layer to a channel layer-proximate layer of said semiconductor material wafer and access vias to said orthogonally oriented source and drain conductive paths; PA1 said defining step including using a combined optical and electron beam lithography sequence; PA1 removing, within said gate window, said gate region aperture uppermost semiconductor layer material; PA1 removing, within said gate window, via portions of said secondary mask dielectric material layer covering uppermost semiconductor material layer-resident portions of said orthogonally oriented source and drain conductive paths; PA1 metallizing, simultaneously within said gate window, pad connections with said uppermost semiconductor layer vertically oriented source and drain conductive paths and a gate element within said small dimension gate region aperture on said channel layer-proximate layer; PA1 said metabolizing step also including depositing a common metal layer over remaining portions of said secondary mask dielectric material layer covering said semiconductor material upper layer and removing selected portions of said deposited metal.
Although each of these documents from the prior art may therefore relate to an aspect of the present invention, it is believed that the invention as described herein represents the first combination of the plurality of concepts and compromises necessary to achieve a successful single metal, non-alloyed contact, inorganic secondary mask-aided, radiation resistant, low power requirement and microwave-capable enhancement mode field-effect transistor.
The above identified previously filed and commonly assigned patent application documents are also of interest with respect to the present invention in the sense that they disclose field-effect transistors of the MESFET and related types and the fabrication of these transistors using single metallization secondary mask-inclusive processing. Notably, however, the transistors of these previously filed and commonly assigned documents are of the n-channel depletion mode type wherein electron charge carriers are utilized and, moreover, these transistors are fabricated through use of diffusion dopings in layers of the transistor rather than controlled implanted dopings in initially non-doped layers as enable the present invention.